Using gate level modeling might not be a good idea for any level of logic design.
使用门级建模对于任何逻辑设计都不是一个好的设计。
The energy optimization methods in circuit level and gate level have been investigated widely.
线路层、门层等低层能量优化方法已经得到广泛研究。
Constant components and output opened ports in the result of high level synthesis lead to explicit redundancy in gate level technology mapping.
高级综合结果中常量元件和输出悬空端口导致门级工艺映射结果中存在显式冗余。
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